TrendForce - MTIA-3 Specifications

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Industry news relevant to tracking AI hardware compute scaling; Meta's MTIA chip progression illustrates the trend of large AI labs developing custom inference ASICs to reduce dependence on Nvidia and scale AI deployment cost-effectively.

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Summary

TrendForce reports that Meta's MTIA-3 AI inference chip is slated for a H2 2026 debut, built on TSMC's 3nm process with GUC handling back-end packaging. The chip features a more complex design than MTIA-2, including extra I/O and an additional SoC, limiting CoWoS packaging yield. This is part of Meta's broader $115–135B 2026 capital spending push into in-house AI ASICs.

Key Points

•MTIA-3 targets H2 2026 launch on TSMC 3nm, with MTIA-2 already in production for H1 2026 debut using CoWoS-S packaging via Broadcom.
•MTIA-3's complex design with extra I/O and additional SoC limits CoWoS packaging to ~8 chips per wafer, necessitating GUC's specialized packaging expertise.
•Meta's 2026 capex is $115–135B, nearly double 2025 spending, with significant allocation toward AI servers and proprietary ASIC development.
•ASIC-based AI servers are projected to reach 27.8% market share in 2026, driven by Google and Meta's in-house chip programs.
•Each MTIA chip reportedly uses ~23 BMC units, expected to benefit Taiwan's ASPEED Technology significantly.

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[News] Meta’s MTIA-3 AI Chip Reportedly Tipped for 2H26 Debut, Built on TSMC 3nm with GUC Support 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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 [News] Meta’s MTIA-3 AI Chip Reportedly Tipped for 2H26 Debut, Built on TSMC 3nm with GUC Support

 
 
 2026-01-30 
 
 Emerging Technologies 
 / Semiconductors 
 
 
 editor 
 
 
 
 
 
 
 
 
 
 
 
 
 As Meta lifts its 2026 capital spending to US$115–135 billion—nearly double its 2025 outlay— CNBC reports that the company’s investment push remains in full swing. Commercial Times notes that Meta’s sustained capex momentum is directly driving stronger demand for AI servers and ASICs (application-specific integrated circuits).

 Amid Meta’s push to develop in-house AI chips, supply chain sources cited by Commercial Times revealed that MTIA-2 is already in production and slated to debut in H1 2026. The chip is built on TSMC’s 3nm process and uses the foundry leader’s advanced CoWoS-S packaging, with compute and I/O design services provided by Broadcom, Commercial Times adds.

 Notably, Commercial suggests that following MTIA-2, MTIA-3 is set for a H2 2026 debut, with TSMC affiliate GUC handling back-end packaging and wafer processing. Despite also using TSMC’s 3nm process and taping out in Q3 2025, MTIA-3 reportedly features a more complex design with extra I/O and an additional SoC. The larger reticle, as per the report, limits CoWoS packaging to just eight chips per wafer, leading Meta to rely on GUC’s expertise for execution.

 TrendForce observes that in the 2026 AI server market, shipment growth will mainly come from North American CSPs, government sovereign cloud projects, and the increasing development of in-house ASICs and edge AI inference solutions by large CSPs. Notably, the share of ASIC-based AI servers is expected to reach 27.8% by 2026, the highest since 2023, as North American firms like Google and Meta expand their own ASIC efforts, according to TrendForce.

 On the other hand, analysts cited by the Commercial Times report also expect Meta’s MTIA chips to significantly boost BMC (Baseboard Management Controller) usage, with each MTIA using around 23 BMC units, benefiting Taiwan’s ASPEED Technology.

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 (Photo credit: Meta)

 
 
 Please note that this article cites information  from Commercial Times  and CNBC . 

 
 
 

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